Phase detectors are mainly used in phase locked loops PLLs. Phase detectors detect periodically the phase difference between an externally generated signal and a reference signal to produce an error signal indicating the phase difference between these two signals. The error signal is used to control the frequency of a voltage/current/digital controlled oscillator producing a signal with which the reference signal is synchronized, so as to bring the clock pulse signal into a predetermined phase or frequency relationship, with the external signal.
Both digital PLLs and mixed PLL use digital phase detectors. Digital phase detectors are known in the art for performing such phase detection. In a digital phase detector, the phase difference can be determined as a measure of the number of clock pulses that occur in the period of the received signal. However, this has the disadvantage that the resolution, that is the accuracy, with which the phase difference can be determined depends on the frequency of the clock pulses used.
U.S. Pat. No. 5,105,160 of Summers describes a phase detector that is adapted to operate in relatively low frequencies such as 15 Khz. The phase detector is comprised of a fine resolution analogue phase detector and a coarse resolution digital phase detector. Referring to FIG. 1, combining circuit 20 receives the output signals DES and AES provided by the digital phase detector and analog phase detector and combines DES and AES to produce a resultant digital output signal DPE. DPE represents an overall indication of the phase difference between an external signal VCS and reference signal PL.
The digital phase detector has an up/down counter 6 for counting clock pulses CPS to determine the number of clock pulses that occur in the time interval between opposite edges of a first signal VCS and one edge of a reference signal PL synchronized with the clock pulses CPS. A latch 7 provides a first digital output signal DES which represents the number.
The analogue phase detector circuit having a flip flop 13 for producing a second signal (VCS') which corresponds to the first signal (VCS) and is synchronized with the clock pulses (CPS). Logic gates (XOR gate 9 and AND gate 10) determine the time intervals between corresponding edges of the first and second signals (VCS,VCS'), and a circuit element determines a phase error voltage (VS) from these time intervals. The circuit element comprises of: capacitor 16. Current source 14 for providing a first current I. A charge switch C_SW 17, being controlled by logic circuit 12, for allowing capacitor 16 to be charged by current I from current source 14, during the time intervals between corresponding edges of the first and second signals to produce the phase error voltage across capacitor 16. A discharge switch DC_SW 18, being controlled by logic circuit 12, for allowing capacitor 16 to be discharged, by a discharge current I/N provided by discharge current source 15. The discharge ends when the voltage across capacitor 16 VC reaches a null value. An amplifier 11 is used to compare VC to 0 and notify logic circuit 12 when it occurs. Logic circuit 12 has a circuit for measuring the number of clock pulses CPS that occur during the discharge period and provide this count AES to combining logic 20. The relation N between the two current sources causes the discharge period to be N times longer than the charge period--the time interval between corresponding edges of the first and second signals, thus providing a resolution that is N times better than the digital phase detector.
A disadvantage of this phase detector is that it is suited to operate in relatively low frequencies. This circuit can not operate in high and very high frequencies. For example, the discharge period, and accordingly the resolution of the analogue phase detector are limited by the frequency of the external signal VCS. In the preferred embodiment of the invention the frequency of VCS is about 15 Khz. Thus, such a phase detector can not be effective when VCS is a high frequency signal.
Furthermore, switching C_SW 17 and CS_SW 18 at high frequency and very high frequency results in a high noise level. Yet another disadvantage results from the digitizing of VS. Yet a further disadvantage of the phase detector is its complexity and it being comprised of several elements, like current sources and an amplifier, that their adaptation to operate in high frequencies is relatively expensive.